Best practices for high-frequency PCB routing

Introduction: why high frequency changes everything

In low-frequency circuits, most routing rules can be treated as simple connectivity problems: just connect the pins correctly and ensure the traces can handle the current. But as signals become faster — whether in clock frequency, edge rate (slew rate), or bandwidth — the printed circuit board ceases to be a passive conductor and becomes an active element of the circuit.

The most important rule of thumb for high-frequency PCB design is this: what matters is not the fundamental frequency of the signal, but the rise and fall times of the edges. A 10 MHz clock with 1 ns edges contains spectral components above 300 MHz. Ignoring this is the cause of most EMI, crosstalk, and signal integrity issues that appear only in the real hardware — never in the simulation.

This article covers the main techniques and rules that every PCB designer needs to master when working with fast digital signals, high-speed interfaces (USB 3.x, PCIe, HDMI, LVDS, DDR), and RF systems. The focus is practical: each concept is accompanied by numerical rules directly applicable in your EDA.

1. Ground planes: the foundation of everything

The ground plane is the most critical element of any high-frequency PCB. It serves as a low-impedance current return path, electromagnetic shielding, impedance reference for transmission lines, and a heat sink. No other routing decision has a greater impact on signal integrity and EMC compliance.

Return current and the lowest impedance path

At low frequencies, return current follows the path of least resistance — typically the shortest path. At high frequencies, it follows the path of lowest impedance, which is the path directly underneath the signal trace. This happens because the mutual inductance between the trace and its return is minimized when the two conductors are superimposed.

The practical consequence is direct: never interrupt the ground plane beneath high-speed traces. Cuts, slots, and holes in the plane force the return current to go around the obstacle, increasing the current loop area, raising the inductance, and generating electromagnetic emissions.

Practical rules for the ground plane

• Dedicate an entire layer to the ground plane in PCBs with 4 or more layers. In 2-layer PCBs, use extensive copper pour on the bottom layer.
• Never route high-speed traces across cuts or slots in the plane.
• When changing layers with a high-speed trace, place an adjacent GND return via (within 300 µm) to maintain the low-impedance return path.
• Avoid splitting the ground plane into analog and digital regions at high frequencies — the connection between the planes creates an inductance that worsens performance. Prefer a single plane with careful routing.

2. Controlled impedance and transmission lines

When a trace behaves like a transmission line, its characteristic impedance (Z₀) must be controlled to avoid reflections. The impedance depends on the trace geometry, the dielectric constant of the substrate (εᵣ), and the distance to the reference plane.

The most common target impedance values are 50 Ω for RF signals and high-speed single-ended interfaces, and 100 Ω differential for pairs like USB, HDMI, PCIe, and LVDS. Any discontinuity in this impedance — stub, via, width change, connector — generates a reflection that degrades the signal.

Calculating trace width for 50 Ω

For a microstrip trace (on the outer layer, over a reference plane), the approximate Hammerstad formula is:

Where h is the dielectric thickness to the reference plane, w is the trace width, and t is the copper thickness. For standard FR4 (εᵣ ≈ 4.3) with a 0.2 mm dielectric, a 50 Ω trace is approximately 0.38 mm wide. Tools like the Saturn PCB Toolkit or the built-in KiCad calculator provide precise values for any stackup.

Vias and stubs: the hidden enemy

Each via introduces parasitic capacitance and, more critically, a stub — the piece of copper that continues beyond the connection point inside the PCB. At frequencies above a few GHz, this stub acts like an antenna that absorbs energy from the signal at the resonant frequency f = c / (4 × stub_length × √εᵣ).

For PCIe Gen 4 and interfaces above 8 Gbps, it is common to specify back-drilling (mechanical removal of the stub) or use blind/buried vias to completely eliminate the problem. For lower frequencies, minimizing the stub depth is already sufficient.

3. Decoupling and power filtering

Decoupling capacitors (bypass capacitors) are the mechanism by which we provide local high-frequency current to components, preventing demand spikes from propagating through the power network and generating noise. Their effectiveness critically depends on positioning and the parasitic inductance of the mounting loop.

Positioning and value selection

The golden rule is: the decoupling capacitor must be as close as possible to the IC power pin, with the GND via adjacent to the VCC via. The inductance of the loop formed by the capacitor, its vias, and the power plane determines the effective resonant frequency — the smaller the loop, the higher the resonant frequency and the better the high-frequency decoupling.

Multi-value strategy

A single capacitor has a series resonant frequency (SRF) above which it becomes inductive. To cover a wide range of frequencies, use multiple capacitors in parallel with different values. The most common combination for high-speed digital ICs is:

4. Routing differential pairs

Differential pairs (like USB, LVDS, PCIe, HDMI) transmit information through the voltage difference between two conductors. The main advantage is immunity to common-mode noise: any interference that affects both conductors equally is canceled at the receiver. For this to work, the two conductors must be geometrically identical.

Rules for differential pairs

• Length matching: the length difference between the two conductors of the pair must be minimal — typically < 5 mil (0.127 mm) for USB/HDMI and < 2 mil for PCIe Gen 4+. Length differences introduce skew, which degrades common-mode rejection.
• Constant spacing: keep the spacing between the two conductors constant throughout the entire path. Spacing variations alter the local differential impedance.
• Route together: the two conductors must be routed on the same layer, side by side, without separation. Never cross one conductor to another layer without crossing the other as well.
• Avoid unnecessary vias: each via adds capacitance and can introduce skew if the two conductors do not change layers at the same point.
• Isolation from other signals: keep at least 3× the pair spacing between the differential pair and other signals to avoid crosstalk.

5. Crosstalk: unwanted coupling between traces

Crosstalk is the transfer of energy from one trace (aggressor) to an adjacent one (victim) through capacitive and inductive coupling. At high frequencies, it is proportional to the frequency, the coupling length, and inversely proportional to the square of the spacing.

There are two types: NEXT (Near-End CrossTalk), measured at the aggressor signal's source end, and FEXT (Far-End CrossTalk), measured at the destination end. For digital signals, FEXT is generally more problematic because it reaches the receiver along with the legitimate signal.

Rules to minimize crosstalk

• 3W rule: keep the spacing between the centers of adjacent traces at least 3 times the trace width. This reduces coupling by approximately 70%.
• Minimize parallel length: reduce the length over which two traces run parallel as much as possible. Cross traces at a 90° angle when they need to cross (on different layers).
• Use reference planes: traces on inner layers with reference planes on both sides (stripline) have significantly less crosstalk than traces on the outer layer (microstrip).
• Guard traces: for highly sensitive analog or RF signals, guard traces connected to GND at multiple points can reduce capacitive crosstalk.

6. High-frequency PCB stackup

The stackup is the most fundamental decision in a high-frequency PCB — and it must be defined before any routing. A well-designed stackup solves much of the impedance, crosstalk, and EMI problems structurally.

For a 4-layer stackup, the most common configuration is: Top (signal) → GND → PWR → Bottom (signal). This ensures that both signal layers have an adjacent reference plane, controlling impedance and minimizing emissions. Avoid the Top/PWR/GND/Bottom stackup, which places the power and ground planes far from the signal layers.

7. EMC considerations in routing

Electromagnetic Compatibility (EMC) is not a final verification step — it is a direct consequence of routing decisions. The main sources of emission in digital PCBs are high-frequency current loops (especially power and clock return loops) and long traces acting as antennas.

Current loop reduction

The power radiated by a current loop is proportional to the square of the frequency, the square of the current, and the square of the loop area. Therefore, reducing the loop area is the most effective measure to reduce emissions. This translates to: keep clock traces close to their GND return, use decoupling capacitors with minimal loops, and avoid long traces for fast signals.

I/O interface filtering

Connectors and external interfaces are the main entry and exit paths for electromagnetic noise. Place ferrite beads in series and filtering capacitors in parallel on I/O lines, positioned as close as possible to the connector. For high-speed interfaces, use ESD components with minimal capacitance (typically < 0.5 pF) so as not to degrade signal integrity.

# .kicad_dru file — custom rules for high-speed signals

(rule high_speed_clearance
  (constraint clearance (min 0.2mm))
  (condition "A.NetClass == 'HighSpeed' || B.NetClass == 'HighSpeed'")
)

(rule differential_pair_gap
  (constraint diff_pair_gap (min 0.1mm) (max 0.15mm))
  (condition "A.NetClass == 'USB_HS'")
)

(rule no_via_in_pad_hs
  (constraint disallow via)
  (condition "A.NetClass == 'RF'")
)

# Minimum width for 50 Ω traces in FR4 0.2mm dielectric
(rule rf_trace_width
  (constraint track_width (min 0.35mm) (max 0.42mm))
  (condition "A.NetClass == 'RF'")
)

8. Review checklist for high-frequency PCBs

Before sending the project to manufacturing, go through this checklist. Each item represents a category of problem that, if not verified, can result in signal integrity failure, EMC issues, or intermittent malfunction.

Conclusion

Routing PCBs for high frequencies is a discipline that combines electromagnetic physics, materials knowledge, and practical experience. The rules presented here are not arbitrary — each has a clear physical justification, and understanding the why is just as important as knowing the what.

The most impactful starting point is always the ground plane: a continuous and well-connected plane solves a large part of the problems even before routing begins. From there, controlled impedance, judicious decoupling, and attention to crosstalk complete the foundation of a robust design.

For critical projects, signal integrity (SI) and PDN simulation before manufacturing are becoming increasingly accessible — tools like HyperLynx, Sigrity, and KiCad itself with simulation plugins allow identifying problems before the hardware is manufactured. The cost of a simulation is always less than that of a PCB revision.